Semiconductor non-volatile memory device having a NAND cell structure

ABSTRACT

A NAND stack array (95&#39;) is placed within a well formed on a semiconductor substrate and includes a series array of memory cell transistors (10) whose threshold voltages can be electrically altered over a range of depletion values. When a cell within a certain NAND stack is selected for a read operation, a peripheral circuit drives selected gate word line to the well potential and drives the word lines of the other gates within the selected NAND stack to a potential at least equal in magnitude to the magnitude of the a reference voltage plus the threshold voltage of a memory cell in the programmed state.

This is the U.S. National Stage Application of PCT/US96/17130, filedOct. 24, 1996. This application claims the benefit of U.S. ProvisionalApplication No. 60/007,063, filed Oct. 25, 1995.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to improvements in semiconductor memoriesand, more particularly, to improvements in electrically erasable,electrically programmable read-only memories used for large capacitydata storage.

2. Description of the Related Art

The demand for portable and hand held devices which require largeamounts of data storage has grown substantially within recent years andis expected to continue to grow well into the next decade. Products suchas digital cameras, cellular telephones, personal organizers, voicerecording devices and palm top personal computers as well as a host ofspecialized remote data collection tools are available today and severalnew products are in development. In nearly all of these products data isstored on solid state electronic media rather than on a hard disk drive,due to the requirements of higher performance, lower energy consumptionand superior ruggedness. However, the cost of a given amount of solidstate storage media has proven to greatly exceed that of hard disk drivesolutions, making it difficult to build attractively priced productswhich contain enough solid state memory to adequately meet the productrequirements.

Recently, a "NAND" type non-volatile memory cell structure has reemergedas a proposed way to reduce manufacturing costs over conventional solidstate storage. Higher storage capacity and lower costs are achieved byutilizing a smaller memory cell composed of a single memory transistorwhich shares each of its nodes with adjacent memory cells. Several suchcells are grouped together in a "NAND stack", with their channels inseries, along with means to connect the stack ends to a bit line and areference line. In the past the non-volatile memory transistor used aMNOS non-volatile element, but more recently, floating gate approacheshave dominated. In either case the small cell size is the key elementwhich enables higher densities and lower costs.

However, floating gate NAND cells have not been able to realize expectedcost reductions due to inherent limitations. Internal write voltages offloating gate NAND memories are typically five to seven times the normalCMOS product power supply limits. Cell sizes are difficult to scale dueto the stacked polysilicon floating gate geometry making manufacturingincreasingly difficult. Threshold voltages are difficult to control,causing long test times and lower product yields. Each of these factorsare intrinsic to the floating gate NAND approach and each significantlyaffects the product cost.

In the past MNOS (Metal Nitride Oxide Silicon) NAND memory arrays wereproposed as a means to realize lower costs. The MNOS structure isconceptually a better approach than the floating gate method, since itis simpler to manufacture, has a naturally tighter threshold voltagedistribution, requires minimal test times, and enables much lower writevoltages. However, the methods proposed for reading and writing MNOSNAND memories progressively weakens the stored data, destroying italtogether prior to the expected life of the product. This problem isreferred to as a "disturb".

Referring now to FIG. 1, current NAND technologies utilize a singletransistor floating gate device 10. The drain (D), gate (G), source (S),and bulk (B) contacts, as well as the floating gate (FG) are labeled.Current flows in a channel region between the drain and source when thedrain and source are at different potentials, and under direct controlof the potential placed on the gate relative to the source and bulk,whose potentials need not be equal. The FG is a non-volatile chargestorage node isolated from and between the gate and the channel region.To erase a memory cell, a large negative gate to bulk potential isformed that couples the layer FG to a negative potential, causing holesto be accumulated in the channel region. These holes can tunnel to theFG by the Fowler-Nordheim effect, because of the large electric fieldsthat result from the large gate to bulk potential. Holes on the FG willerase the memory cell to shift the threshold in a negative direction toprovide a logic "0" stored state.

To program the memory cell, a large positive gate to bulk potential isformed that couples the FG to a positive potential and inverts thechannel region with electrons. As with holes, the electrons can tunnelto the FG by the Fowler-Nordheim effect. The threshold voltage of thememory transistor shifts in the positive direction to provide a logic"1" state.

Conventional NAND technologies are designed such that erased memorycells have depletion thresholds and programmed memory cells haveenhancement thresholds. More specifically, the depletion state thresholdvoltage is achieved when the gate voltage is negative with respect tothe source node and the enhancement state threshold voltage is achievedwhen the gate voltage is positive with respect to the source node. Whenwritten, these negative and positive thresholds have a fairly broaddistributions, typically in the 1.5-2.0 volt range.

A conventional NAND stack 20 is shown in FIG. 2, where sixteen (16)non-volatile memory cells 10 (MC0-MC15) are placed in series with twon-channel select transistors 11 and 12, transistor 11 being placed atthe drain side (MSD) and transistor 12 being placed at the source side(MSS) of the memory transistors 10. Except for memory transistors MC0and MC15, the drain and source of adjacent memory cells are connectedtogether. The source of memory transistor MC0 is connected to the drainof the next memory cell down, memory transistor MC1. Also, the drain ofmemory transistor MC0 is connected to the source of memory transistorMSD and the drain of memory transistor MSD is connected to the metal bitline (BL). The drain of memory transistor MC15 is connected to thesource of the next memory cell above, memory transistor MC14. Also, thesource of memory transistor MC15 is connected to the drain of selecttransistor MSS and the source of select transistor MSS is connected tothe common reference line (CSL), which is typically a diffusion.

It should be noted that the NAND stack unit can be replicated in boththe BL direction (column) and orthogonal to the BL direction (row) toform NAND stack arrays of various sizes. NAND stack units in a columnconnect to a single BL while gates of memory cells within a stackconnect to word lines (WL). The gates of the two select transistorsconnect to select lines (SSL and GSL). The WL's, SSL and GSL runorthogonal to the BLs and are typically formed of polysilicon or amultilayer composite, generally including a silicide on polysilicon. Thefirst memory cells (MC0's) in NAND stack units along the same row areconnected to WLO and the last memory cells (MC15's) in NAND stack unitsalong the same row are connected to WL15. This is also true for theother memory cells and the select devices in NAND stack units along thesame row.

During reading of the selected memory cell, a current path must bemaintained from the selected memory cell to the CSL and BL connectionsof the NAND stack. Each of the fifteen non-selected NAND cells in theselected NAND stack are rendered conductive by applying sufficient gateto source voltage to not only overcome the positive enhancementthreshold voltage but also to provide for a high level of conductance.Then with the gate of the selected memory cell and the CSL of the NANDstack set to ground, the state of the selected cell can be determined bysensing current flow through the selected NAND stack. When the selectedmemory cell has a negative depletion threshold, current will flowthrough the NAND stack, and when the selected memory cell has a positiveenhancement threshold, little or no current will flow through the NANDstack.

Examples of read, erase and program operation bias schemes are shown inFIG. 3, according to conventional NAND approaches. These biases areapplied during a time in which the operation achieves the desiredresult. A complete wave form diagram would show the conditions beforeand after these biases as well as the time periods; however, only thechange affecting bias conditions are shown here. The read biases aretypically active for periods of tens to thousands of nanoseconds and theerase and program biases are active for periods of 100 microseconds toseconds. The amount of time depends on the device size and theperformance objectives of the product.

Referring now to FIG. 4, during a read operation, the reference line CSLis at the same potential as the bulk of the NAND transistors, or V_(s)=ground. The gates of the memory cells in the path of the selected celland the two select devices are boosted to 4.5 v, and the gate of theselected memory cell is left at the CSL potential. The 4.5 v potentialis used, first, to overcome the positive enhancement program thresholdson unselected memory cells, and, second, to achieve suitable conduction.Achieving the second objective depends on the number of unselecteddevices within the selected NAND stack which are in the positiveenhancement program state, which can be anywhere from zero to fifteen.The condition that requires the most gate voltage is that in which theselected memory cell, say MC1, is erased to a negative threshold and allof the unselected memory cells have a high positive threshold and the BLpotential is low, say at 1 volt. In this situation, the erased selectedmemory cell has 0 volts on its gate WL1 and is sinking current from theBL, and the unselected memory cell at the top of the NAND stack (e.g.MC0) has a program threshold. To maintain sufficient conduction throughthe unselected memory cell, its gate voltage applied to WL0 must be atleast V_(g) =V_(tp) +V_(s) +V_(on), where V_(tp) is the enhancementprogram threshold voltage of MC0, V_(s) is the source voltage on MC0 andV_(on) is the additional voltage required to achieve sufficientconductivity.

More specifically, when V_(tp) is 2.0 volts, V_(s) is very near the BLvoltage of 1.0 volt and V_(on) should be at least 1.5 volts, so V_(g)≧4.5 volts. A Vg potential of 4.5 volts or higher would require internalboosting above V_(cc) when the nominal supply voltage V_(cc) is lessthan 4.5 volts. This is highly disadvantageous when attempting tooptimize device read performance in today's products where V_(cc) istypically 3.3 volts or below. During a read operation, the time andpower required to boost fifteen word lines to 4.5 volts and the twoselect lines can be substantial. Since the word lines and select linesrun completely across the NAND structured memory array, the amount ofcapacitance that must be boosted to 4.5 volts could be on the order oftens and possibly hundreds of picofarads. Even though this is readilydone on today's NAND devices, a method for reading that does not includeboosting would be extremely beneficial.

It can be seen that during a read operation, the gate to sourcepotential is greatest on MC15, the memory cell closest to the groundedCSL reference line. If the selected cell is in the conductive erasedstate, current will flow through the NAND stack; however, there will belittle voltage loss between the source of MC15 and the reference lineCSL since the selection device MSS is biased well on. Further, if theselected device were in the non-conductive program state, then verylittle or negligible current would flow through the NAND stack, and thegate to source voltage on MC15 would be nearly exactly equal to the gatevoltage on WL15. Thus, the gate to source voltage on MC15 is for allpractical purposes equals the voltage on WL15 during read operations.

Furthermore, when reading a NAND device, the address pattern will notnecessarily follow a preset sequential pattern, but rather might followa random or frequently favored partial pattern. Therefore, there is noassurance that each of the rows within a NAND stack will be read insequence, nor is there assurance that they will ever be read. A worstcase analysis would include the condition that only the MC0 is read, andthat it is always in the enhancement programmed state. Under thisconfiguration, little or negligible current will flow, and the gate tosource voltage on MC1 through MC15 will be nearly equal to their wordline voltages. Thus, under worst case conditions, the gate to sourcevoltage on MC1 through MC15 is equal to the worst case gate to sourcevoltage described above for MC15 during typical read operations.

Therefore, when the device is set in a data read mode under worst caseconditions, a gate to source bias is applied to transistors MC1 throughMC15 within a selected NAND stack. The bias is expected to be V_(g)≈V_(tp) +V_(s) +V_(on) applied during each and every read. As shown inFIG. 3 the gate to source voltage applied to a selected word line duringa program mode is of the same polarity as the voltage applied to anunselected word line during a read mode. Even though the program modevoltage is much greater than that used during the read mode, continuousreading during the expected life of the part can cumulatively disturbthe stored data much as if it were in the program mode. This disturbproblem is manageable if the gate to source voltage is much smaller thanthat used to program the device. However, this requires that the gate tosource voltage be as small as possible or that the program voltage bevery large. Neither is desirable and ultimately product performance orreliability must be compromised.

The method employed in NAND devices for programming memory cells is onethat programs a single WL at a time. Page buffers are first loaded withdata one byte at a time until the desired data is present and then theWL is brought to a high level (V_(pp)), typically in the 15.5 to 20 voltrange. To program a memory cell to a high threshold voltage, 0 volts istransferred to the BL from the data buffer prior to placing Vpp on theselected WL. This creates a high positive gate to channel electric fieldthat causes electrons to tunnel to the FG shifting the threshold voltagepositively.

There are two methods primarily used to inhibit the programming ofmemory cells on the selected word line when using "program inhibit"mode. The first is a method known as "selfboosting". The second is amethod using a relatively high inhibit voltage on the bit lines. Withthe self boosting program inhibit method, unselected WL's are raised to10 volts and the selected WL is raised to 15 to 20 volts. When thesenodes are raised, capacitance between these nodes and the NAND stackchannel regions causes the channel potential to rise. Once the NANDstack channel is capacitively coupled above V_(cc) in the self-boostingmethod, V_(cc) is held on the desired BL and on SSL to cut-off the topselect device of the NAND stack. Then the channel potential in the NANDstack continues to rise by the capacitive coupling and all the channelregions are coupled to approximately 8 volts to inhibit the programmingon the selected WL. In program inhibit method, 8 volts from a latch inthe data buffer is placed on the BL associated with the selected WL.This 8 volts is then transferred through the MSD and memory transistorsto the channel regions of all memory cells in the NAND stack containingthe selected WL which inhibits programming. While programming or programinhibiting, all voltages are above ground.

With either program mode method, the unselected word line voltage is atten (10) volts. When the selected transistor is to be programmed, zerovolts is supplied by the bit line to the channel regions of thetransistors within the NAND stack. Even though the program mode voltageis used far less often than the read mode, the voltage is much higherand a minimal amount of program operations can cumulatively disturb thestored data. Ultimately product performance or reliability must becompromised to accommodate this high voltage.

The method used to erase the memory cells in the NAND stack is a bulkmethod that erases all memory cells connected to the same bulkconnection. The gates of all memory cells are held at 0 volts and thebulk is then taken to 21 volts.

As integrated circuit technology advances to smaller geometries andlower operating voltages, it becomes increasingly difficult toaccommodate the large voltages required to program and eraseconventional devices. Larger than normal geometries and special devicestructures are required to switch and route the program voltages,ultimately resulting in high final product costs. It is desirable toreduce program voltages in order to improve costs and reliability. Suchreduction are limited, however, by the read disturb problem describedbefore. As program voltages are lowered, read voltages becomeincreasingly disturbing.

Therefore, during read and write operations, NAND cell structuresrequire the application of voltage to memory cell gates within the NANDstack to render them conductive and to provide a clear current path tothe selected memory cell within the stack. Currently, the applied gateto source voltage on the cells in the path must be of sufficientmagnitude to not only overcome an enhancement threshold voltage in theNAND stack cells but also enough to provide sufficient inversion toachieve acceptable current flows. The combined objectives requires agate to source voltage greater than that which can be reliably usedwithout creating a disturb problem in read and program modes or withoutrequiring internal voltage boosting in read mode.

Therefore, without further innovation the low cost advantages of theNAND approach cannot be used without significantly limiting the numberof operations to minimize the effect of disturbs. Further voltages willremain higher than desired and disturb effects will also complicatefloating gate product designs.

SUMMARY OF THE INVENTION

In light of the above, therefore, it is an object of the invention toprovide an improved non-volatile semiconductor memory device thatprovides better data storage reliability compared to prior art devices.

It is another object of the invention to provide an improvednon-volatile semiconductor memory device that can be read asubstantially higher number of times without loss of data compared toprior art devices.

Another object of the invention is to provide an improved non-volatilesemiconductor memory device that can be written a substantially highernumber of times without loss of data compared to prior art devices.

It is further an object of the invention to provide an improvednon-volatile semiconductor memory device that achieves better readperformance by eliminating the need to internally boost potentialsbeyond the supply voltage V_(cc) during a read operation.

It is yet another object of the invention to provide an improvednon-volatile semiconductor memory device that provides highermanufacturability by reducing gate voltages during read and writeoperations.

Yet another object of the invention is to provide an improvednon-volatile memory device that realizes smaller chip size byeliminating the transistor between the bit line and the NAND stack.

It is still further another object of the invention to provide animproved non-volatile memory device that can be produced at lower costsby reliably utilizing a dielectric charge storage.

The above and further objects, details and advantages of the inventionwill become apparent from the detailed description of the preferredembodiments presented hereinafter, when read in conjunction with theaccompanying drawings.

According to the present invention, there is provided a NAND stack arrayon a semiconductor substrate of a first conductivity type, a well areaof a second conductivity type in the substrate, parallel bit linesformed over the semiconductor region oriented in a first direction,parallel word lines oriented in a second direction over thesemiconductor region beneath the bit lines, reference line segments of afirst conductivity type in the surface of the well and oriented thesecond direction, and re-writeable NAND stacks, forming "NAND stackarrays," connected on one end to bit lines and on the opposite end toreference line segments. The NAND stack is placed within the well andincludes a series array of memory cell transistors whose thresholdvoltages can be electrically altered over a range of depletion values.The memory cell transistors include a pair of source and drain regionsof a first conductivity type formed in the surface of the semiconductorregions within the well, a control gate, and a charge accumulationlayer, such as a layer of silicon nitride or a floating gate, formed tocover the semiconductor area between the source and drain regions. Thewell area provides junction isolation between the bias applied to thebulk of the memory transistors and the bias applied to other circuitrywithin the non-volatile semiconductor memory in regions peripheral tothe NAND stack array. Peripheral circuits include a driving circuit forbiasing the reference line segments to a potential within the range offrom the well potential to at least the supply potential Vcc, such asVoff, during read operations. When a cell within a certain NAND stack isselected for a read operation, a second peripheral circuit drives theselected gate word line to the well potential and drives the word linesof the other gates within the selected NAND stack to a potentialincluded within the range of V_(off) to V_(cc).

BRIEF DESCRIPTION OF THE DRAWINGS

In the detailed description of preferred embodiments of the inventionpresented below, reference is made to the accompanying drawings ofwhich:

FIG. 1 shows a schematic representation of a floating gate NAND memorytransistor according to the prior art;

FIG. 2 illustrates the internal arrangement of a floating gate NANDmemory stack according to the prior art;

FIG. 3 shows the conventional biases applied to the NAND stack duringread, erase and program operations according to the prior art;

FIG. 4 illustrates the biases applied to a NAND memory stack under theworst case gate voltage disturb condition during a read operationaccording to the prior art;

FIG. 5 shows a typical plot of threshold voltage distributions of NANDmemory cells within a NAND stack array according to a preferredembodiment of the present invention;

FIG. 6 schematically shows the overall circuit arrangement of the NANDstack cell memory circuit according to a preferred embodiment of thepresent invention;

FIG. 7 schematically shows the internal circuit arrangement of a NANDconfigured non-volatile memory according to a preferred embodiment ofthe invention using a floating gate charge accumulation layer;

FIG. 8 schematically shows the an internal circuit arrangement of a NANDconfigured non-volatile memory according to another preferred embodimentof the invention using a floating gate charge accumulation layer;

FIG. 9 is a table showing example biases applied to the NAND stackduring read, erase and program operations according to a preferredembodiment of the invention;

FIG. 10 illustrates the wave forms of main electrical signals appearingin main portions of the NAND stack having the schematic of FIG. 6 duringvarious modes of operation;

FIG. 11 shows a schematic representation of a NAND memory transistorutilizing a silicon nitride dielectric charge accumulation layer;

FIG. 12 is a schematic showing an internal circuit arrangement of a NANDconfigured non-volatile memory according to another preferred embodimentof the invention using a silicon nitride dielectric charge accumulationlayer;

FIG. 13 shows a table of example biases applied to the NAND stack duringread, erase and program operations according to another preferredembodiment of the invention;

FIG. 14 shows a typical plot of threshold voltage as a function ofdecades of time of NAND memory cells within a NAND stack array accordingto a preferred embodiment of the present invention;

FIG. 15 schematically shows the overall circuit arrangement of the NANDstack cell memory circuit according to another preferred embodiment ofthe present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

According to a preferred embodiment of the invention, a device isprovided that shifts all program and erase threshold voltages tonegative depletion values. As seen in FIG. 5, program threshold voltagedistributions within the new device range from V_(tpmax) to V_(tpmin)and erase threshold voltage distributions range below V_(temax). In allinstances, the threshold voltage refers to the gate voltage of atransistor measured relative to the source of that same transistor, inaccordance with industry standards. The shape of the program and erasethreshold voltage distributions are for illustration purposes, and maydiffer from the actual shapes of the distribution, which are highlytechnology dependent. All threshold voltages mentioned above satisfy thefollowing condition of 0 volts>V_(tpmax) >V_(tpmin) >V_(temax). Typicalvalues for those values may be V_(tpmax) =-0.5 v, V_(tpmin) =1.5 v, andV_(temax) =-2.0 v.

Referring additionally now to FIG. 6, a non-volatile memory deviceaccording to a preferred embodiment of the invention has a memory array90 which includes at least two blocks 95, each block 95 being at leastone, and preferably more than one NAND stack units in height. Variousembodiments of the NAND stacks within the blocks 95 in FIG. 6 aredescribed in detail below. Associated with each block 95 are the rowdecoders 92 that drive lines 801 across the width of the blocks 95,including word lines, WL, global select line, GSL, and an optional stackselect lines, SSL. The use of these lines 801 within block 95 are shownin greater detail below. The blocks 95 are linked together by the bitlines 800 that also go to the page sense amplifiers, buffers and columndecoders 94. Further, blocks 95 are linked together in common by commonsource line 810 which forms a common reference node, hereinafter calledCSL, whose voltage is generated and controlled by reference generator96.

Reference generator 96 is required since the voltage on the CSL is notequal to ground potential during read modes as will be described indetail later. Predecoded row address selection information is suppliedto row decoders 92 by the row predecoder 91 by way of the predecoded rowaddress bus 803. Row address lines 802 supply row input addressinformation to row predecoders 91 and likewise column address lines 804provide column input address information to column decoders included in94. An erase/program control unit 93 is included which is controlled bywrite control lines 809 to supply V_(neg1) 806 to the row decoders 92,V_(neg2) 808 to the page sense amps, buffers and column decoders unit94, and V_(pw) 807 to the memory array 90. Data input and output isperformed by way of data line 805.

FIG. 7 and 8 show two NAND stacks embodiments 95' and 95", respectively,which are be used in the device shown in FIG. 6. As shown in FIG. 7,block 95' includes (n+1) copies of the NAND stack 30 according to afirst embodiment of the invention. Each NAND stack 30 is connected atthe top to one of (n+1) bit lines, BL0, BL1, through BLn and connectedon the bottom to the common source line, CSL. Further, the entire block95' resides within a common well connected to V_(pw). The NAND stack 30includes a number of non-volatile transistors 10 as described above forFIG. 1. Typically the number of transistors 10 equals a power of twowhen used to store binary data, and in FIG. 7 sixteen transistors,labeled MC0, MC1, through MC15, are shown as an example embodiment. Thegates of transistors MC0, MC1, through MC15 are connected in common withgates of adjacent NAND stacks within block 95' by way of word lines WL0,WL1 through WL15, respectively. The NAND stack 30 also includesselection transistors MSD and MSS whose gates are connected in commonwith adjacent NAND stacks within block 95' by way of stack select lineSSL0 and global select line GSL0. Selection transistor MSD could includea non-volatile transistor.

Referring now to FIG. 8, block 95" includes (n+1) copies of the NANDstack 40 according to a second embodiment of the invention. Each NANDstack 40 is connected at the top to one of (n+1) bit lines, BL0, BL1,through BLn and connected on the bottom to the common source line CSL.Further, the entire block 95" resides within a common well connected toV_(pw). The NAND stack 40 is composed of a number of non-volatiletransistors 10 as described above for FIG. 1. Typically, the number oftransistors 10 equals a power of two when used to store binary data, andin FIG. 8 sixteen transistors, labeled MC0, MC1, through MC15, are shownas another example embodiment. The gates of transistors MC0, MC1,through MC15 are connected in common with gates of adjacent NAND stackswithin block 95" by way of word lines WL0, WL1, through WL15,respectively.

The NAND stack 40 also includes a selection transistor MSS whose gate isconnected in common with adjacent NAND stacks within block 95" by way ofthe global select line, GSL0. The primary difference between the twoNAND stacks 30 and 40 in FIGS. 7 and 8 is that the transistor MSD inFIG. 7 is a depletion device with a threshold near -1.5 v or eliminatedfrom the NAND stack as in FIG. 8. The depletion transistor MSD waschosen or completely eliminated to minimize voltage drops. All the biasmethods used in the new device of this invention allow the depletiontransistor MSD device to be optional. The transistor MSD device would beused optionally to decrease the capacitance of the bit line, BL.

Referring additionally to FIG. 9, the NAND stack utilizes a read biasscheme, in which, with all negative threshold voltages, gates ofunselected memory cells can be placed at V_(g),on which is at leastequal in magnitude to the magnitude of V_(off) plus the maximum programstate threshold voltage (V_(off) +V_(tpmax)). The selected memory cellcan have a gate at the well potential, in this case V_(s) =ground. Asubstrate containing the well can be connected to a supply voltage, suchas V_(cc). Alternatively, a second well containing the first well can beconnected to a supply voltage, such as V_(cc), while the substrate is atthe well potential. For the purpose herein it is assumed that V_(g),on=V_(cc). With the gate of the selected memory cell at 0 volts and theprogram and erase threshold voltages all negative, the common referenceline, CSL, needs to be above the gate potential to turn off a selectedcell that is programmed, while keeping on one that is erased. Forexample, if a programmed memory cell transistor has a first thresholdvoltage and an erased memory cell has a second threshold voltage, thecommon reference line CSL can have a potential with a magnitude that isat least equal to the first threshold voltage. The voltage relative tothe well on the common reference line, CSL, necessary to turn offselected programmed memory cells and keep on selected erased memorycells is V_(off) and is defined by |V_(tpmin) |<V_(off) <|V_(temax) |.With the values of V_(tpmin) =-1.5 volts and V_(temax) =-2.0 volts, thevalue of V_(off) could be 1.8 volts.

During reading, the transistors MSD and MSS in FIGS. 7 and 8 arerendered conductive by placing V_(cc) on their gates by way of linesSSL0 and GSL0, respectively. Likewise each of the unselected devices arerendered conductive by placing V_(g),on on their gates by way of theirrespective word lines. Adequate conductivity between the selected memorycell and the bit line, BL, and common reference line, CSL, connectionsmust exist so that the state of the selected memory cell can bedetermined. If the selected memory cell is programmed, very little ornegligible current flows through the NAND stack and the bit line, BL,voltage initially at V_(cc) will stay at or near V_(cc). When theselected memory cell is erased, current will flow from the bit line, BL,to common reference line, CSL, and the bit line, BL voltage will droptoward V_(off). V_(tpmax) can then be defined to be the amount ofnegative threshold necessary to ensure adequate conduction through theNAND stack when all unselected memory cells are programmed to V_(tpmax)and the erased selected memory cell is of minimal conductance atV_(temax).

More specifically, when reading the state of transistor MC1, word line,WL1, is placed at the well potential, in this case V_(s) =ground, whileall other word lines are at V_(g),on, in this case chosen to be V_(cc),rendering them conductive. A substrate containing the well can beconnected to a supply voltage, such as V_(cc). Alternatively, a secondwell containing the first well can be connected to a supply voltage,such as V_(cc), while the substrate is at the well potential. Further,common reference line, CSL, is at V_(off) =1.8 volts and the bit linepotential on BL0 is placed at V_(cc). If memory transistor MC1 is erasedwith a depletion threshold voltage of magnitude greater than V_(off),memory transistor MC1 will be conductive, allowing current flow throughthe NAND stack and the potential of the bit line, BL, will fall fromV_(cc) toward V_(off). If memory transistor MC1 is programmed with adepletion threshold voltage of magnitude less than V_(off), memorytransistor MC1 will be non-conductive impeding current flow through theNAND stack and the potential of the bit line, BL, will remain equal ornearly equal to V_(cc). The state of the selected cell can be determinedby sensing the voltage on the bit line, BL, using conventional sensingmeans. It is now apparent that the device according to the inventionperforms a read mode operation with substantially lower voltages.

With respect to read disturbs in unselected devices, during reading, thechannel region of unselected memory cells in the NAND stack will beclose to the voltage of the common reference line, CSL, of V_(off) underworst case conditions, rather than at ground as in the conventionalapproach. Further, the gate voltage value of V_(g),on will be no greaterthan V_(cc) in the example given above, rather than boosted above V_(cc)in contrast to that of a conventional device. Thus, the gate to channelregion voltage in the device of the invention would be V_(cc) -V_(off),rather than greater than V_(cc). Using the specific conditions discussedabove where V_(cc) =3.3 volts and V_(off) =1.8 volts, the gate to sourcevoltage of this invention will be 1.5 volts. This gate to source voltagewill produce significantly less disturb than the gate to source voltageof 4.5 volts used in the conventional device. Even if the conventionaldevice used only V_(cc) =3.3 volts on the unselected devices, the gateto source voltage would still be over two times greater than that usedby the device of this invention. It is now also apparent that the readmode of the device of the invention uses less gate to source voltage onunselected devices, producing substantially less read disturb.

The read bias scheme also works with a deselection method, where all thegates of the memory cells and the select transistor in the NAND stackare brought to the well potential. With this deselection method, whenthe NAND stack is selected, fifteen word lines, WLs, and the signals onlines GSL and SSL are all driven to V_(cc). As noted earlier, thefifteen word lines, WLs, with the lines GSL and SSL could represent tensand possibly hundreds of picofarads of loading. Though the problem ofboosting above V_(cc) does not occur with this read bias scheme, it willbe appreciated that driving all that loading could be a problem.

According to one method of deselection, all word lines, WLs, in the NANDstack are deselected high with only the signals on lines GSL and SSLbeing low to cut-off the current path from the bit line, BL, to thecommon reference line, CSL, since all word lines, WLs, are high onmemory cells with negative thresholds. A selected word line, WL, in thiscase will be brought to ground while the lines GSL and SSL are broughthigh to activate the NAND stack.

The method chosen to erase memory cells in the NAND stack enables singleword lines, WLs, to be erased. This is done to have smaller sector sizesand the flexibility to erase and program single word lines, WLs, if"refreshing" of non-volatile states is necessary. The idea of"refreshing" will be discussed later. FIG. 9 shows the biasing in termsof defined variables for erasing as well as programming, and all biasingis valid for the NAND stack with or without the transistor device MSD.

To erase a single row, the selected row is pumped to a negativepotential, V_(nege), while the p-well (bulk) is placed at V_(cc). Thep-well is never brought above V_(cc) so that either a single p-well inan n-type substrate or a p-well nested within a n-well on a p-typesubstrate can be used with this invention. To erase inhibit, word lines,WLs, which are not selected are also brought to the same V_(cc)potential as the p-well. The high negative potential on selected wordlines, WLs, causes holes to be accumulated in the selected transistorchannel regions. The electric field in the selected memory transistorscauses the holes to tunnel to the floating gate, FG, which shifts theirthreshold voltage negatively to the erased state. This erase mode canalso be effected on several word lines at once by use of appropriateword line decoding.

With reference additionally now to FIG. 10, in the program mode theselected word line, WL, is placed at V_(cc), and then the p-well (bulk)is pumped to a negative potential, V_(negpw). At the same time thep-well is being pumped, the bit line, BL, associated with the memorycell to be programmed is pumped to V_(negp). The value of V_(negpw) ispreferably less than or equal to the value of V_(negp). The differencein Vnegpw and V_(negp) is used to back bias the field device betweenadjacent NAND stacks in a row to increase the field breakdowncharacteristics. The high positive gate to channel region potential inselected memory transistors inverts the channel region with electronsand the electric field causes the electrons to tunnel to the floatinggate, FG, shifting the threshold voltage positively to the programmedstate. To inhibit programming of memory cells with its gate at V_(cc),the bit lines, BLs, associated with memory cells to be inhibited arelowered to an inhibit voltage, V_(inh), at the same time the p-well islowered. For most technologies, V_(negpw) and V_(negp) are below 0volts, and V_(inh) is usually about halfway between V_(cc) and V_(negp).All deselected word lines, WLs, are lowered to V_(negpw) to stopprogramming on deselected word lines, WLs.

Referring now to the schematic representation in FIG. 11, anotherpreferred embodiment of the invention utilizes a SONOS (poly-siliconoxide silicon-nitride oxide silicon) memory transistor 11. The drain(D), gate (G), source (S) and bulk (B) contacts as well as theoxide-nitride-oxide layer (ONO) are labeled in the drawing. Currentflows in a channel region between the drain and source when the drainand source are at different potentials, and under direct control of thepotential placed on the gate relative to the source and bulk whosepotentials need not be equal. The SONOS technology stores charge intraps in the silicon nitride layer and/or a silicon oxynitride layerrather than in a floating gate. To erase a memory cell, a large negativegate to bulk potential is formed that accumulates the channel regionwith holes. These holes can tunnel by the Fowler-Nordheim effect to thesilicon nitride because of the large electric fields that result fromthe large gate to bulk potential. Holes in the silicon nitride willerase the memory cell to shift the threshold in a negative direction toprovide a logic "0" stored state. To program the memory cell, a largepositive gate to bulk potential is formed that inverts the channelregion with electrons. As with holes, the electrons can tunnel by theFowler-Nordheim effect to the silicon nitride. The threshold voltage ofthe memory transistor shifts in the positive direction to provide alogic "1" state.

As shown in FIG. 12, another preferred embodiment of the invention shownin FIG. 6 uses a NAND stack 50 with SONOS devices 11 without a selecttransistor, MSD. A detailed schematic of block 95'" includes (n+1)copies of the NAND stack 50. Each NAND stack 50 is connected at the topto one of (n+1) bit lines, BL0, BL1, through BLn and connected on thebottom to the common source line, CSL. Further, the entire block 95'"resides within a common well connected to V_(pw).

The NAND stack 50 includes a number of non-volatile transistors 11 asdescribed above with regard to FIG. 11. Typically, the number oftransistors 11 equals a power of two when used to store binary data, andin FIG. 12 sixteen transistors, labeled MC0, MC1, through MC15, areshown as an example embodiment. The gates of transistors MC0, MC1,through MC15 are connected with gates of adjacent NAND stacks withinblock 95'" by way of word lines WL0, WL1, through WL15, respectively.

The NAND stack 50 also includes a selection transistor MSS, whose gateis connected in common with adjacent NAND stacks within block 95'" bythe global select line, GSL0. The primary difference between the twoNAND stacks 40 and 50 in FIG. 8 and FIG. 12 is the choice of memorytransistor, 10 or 11 respectively. The transistor MSD shown in FIG. 7could be used optionally in the NAND stack using memory transistor 11 todecrease the capacitance of the bit line, BL. In this case thetransistor MSD could be either a conventional field effect transistor ora SONOS field effect transistor.

Referring additionally now to FIG. 13, biases according to thisinvention are shown using with V_(cc) =3.0 volts for a floating gate,FG, embodiment and for a SONOS embodiment. The floating gate, FG,embodiment is included for comparison, contrasting the significantlylower erase and program voltages of the SONOS embodiment.

With all negative threshold voltages, gates of unselected SONOS memorycells can be placed at V_(g),on, which is at least equal in magnitude tothe magnitude of V_(off) plus the maximum program state thresholdvoltage (V_(off) +V_(tpmax)). The selected SONOS memory cell whose gateis at the well potential, in this case V_(s) =ground. A substratecontaining the well can be connected to a supply voltage, such asV_(cc). Alternatively, a second well containing the first well can beconnected to a supply voltage, such as V_(cc), while the substrate is atthe well potential. It is assumed that V_(g),on =V_(cc). With the gateof the selected memory cell at 0 volts and the program and erasethreshold voltages all negative, the common reference line, CSL, needsto be above the gate potential to turn off a selected cell that isprogrammed while keeping on one that is erased. The voltage relative tothe well on the common reference line, CSL, necessary to turn offselected programmed memory cells and keep on selected erased memorycells is V_(off) and is defined by |V_(tpmin) |<V_(off) <|V_(temax) |.With the values of V_(tpmin) =-1.5 volts and V_(temax) =-2.0 volts, thevalue of V_(off) could be 1.8 volts.

During reading, the transistor MSS in FIG. 12 is rendered conductive byplacing V_(cc) on its gate by way of line GSL0. Likewise each of theunselected devices are rendered conductive by placing V_(g),on on theirgates by way of their respective word lines. Adequate conductivitybetween the selected memory cell and the bit line, BL, and the commonreference line, CSL, exist so that the state of the selected memory cellcan be determined. If the selected memory cell is programmed, verylittle or negligible current flows through the NAND stack and thevoltage of the bit line, BL, initially at V_(cc) will stay at or nearV_(cc). When the selected memory cell is erased, current will flow fromthe bit line, BL, to the common reference line, CSL, and the voltage ofthe bit line, BL, will drop toward V_(off). V_(tpmax) can then bedefined to be the amount of negative threshold necessary to ensureadequate conduction through the NAND stack when all unselected memorycells are programmed to V_(tpmax) and the erased selected memory cell isof minimal conductance at V_(temax).

More specifically, when reading the state of SONOS transistor MC1, theword line WL1 is placed at the well potential, in this case V_(s)=ground, while all other word lines are at V_(g),on, in this case chosento be V_(cc), rendering them conductive. Further, the common referenceline, CSL, is at V_(off) =1.8 volts and the bit line potential on lineBL0 is placed at V_(cc). If memory transistor MC1 is erased with adepletion threshold voltage of magnitude greater than V_(off), thememory transistor MC1 will be conductive, allowing current flow throughthe NAND stack and the potential of the bit line, BL, will fall fromV_(cc) toward V_(off). If memory transistor MC1 is programmed with adepletion threshold voltage of magnitude less than V_(off), the memorytransistor MC1 will be non-conductive, impeding current flow through theNAND stack and the potential of the bit line, BL, will remain equal ornearly equal to V_(cc). The state of the selected cell can be determinedby sensing the voltage on the bit line, BL, using conventional sensingmeans.

The method to erase SONOS memory cells in the NAND stack enables singleword lines, WLs, to be erased. This is done to have smaller sector sizesand the flexibility to erase and program single word lines, WLs, if"refreshing" of non-volatile states is necessary, as discussed below.

FIG. 13 shows the biasing in terms of defined variables for erasing, aswell as programming. All biasing is valid for the NAND stack with orwithout the transistor, MSD. To erase a single row, the selected row ispumped to a negative potential, V_(nege), while the p-well (bulk) isplaced at V_(cc). The p-well is never brought above V_(cc) so thateither a single p-well in an n-type substrate or a p-well nested withina n-well on a p-type substrate can be used with this invention.

To erase inhibit word lines which are not selected, deselected wordlines are also brought to the same V_(cc) potential as the p-well. Thehigh negative potential on selected word lines accumulates holes in theselected transistor channel regions. The electric field in the selectedmemory transistors causes the holes to tunnel to traps in the siliconnitride, which shifts their threshold voltage negatively to the erasedstate. This erase mode can also be affected on several word lines atonce by use of appropriate word line decoding.

As shown in FIG. 13 and FIG. 10, in the program mode the selected wordline, WL, is placed at V_(cc) and then the p-well (bulk) is pumped to anegative potential, V_(negpw). At the same time the p-well is beingpumped, the bit line, BL, associated with the SONOS memory cell to beprogrammed is pumped to V_(negp). The value of V_(negpw) is preferablyless than or equal to the value of V_(negp). The difference in V_(negpw)and V_(negp) is used to back bias the field device between adjacent NANDstacks in a row to increase the field breakdown characteristics. Thehigh positive gate to channel region potential in selected SONOS memorytransistors inverts the channel region with electrons and the electricfield causes the electrons to tunnel to the traps in the siliconnitride, shifting the threshold voltage positively to the programmedstate.

To inhibit programming of SONOS memory cells with its gate at V_(cc),the bit lines associated with SONOS memory cells to be inhibited arelowered to an inhibit voltage, V_(inh) at the same time the p-well islowered. For most technologies, V_(negpw) and V_(negp) are below 0volts, and V_(inh) is usually about halfway between V_(cc) and V_(negp).All deselected word lines, WLs, are lowered to V_(negpw) to stopprogramming on deselected word lines.

Specifically, in writing a programmed state in memory transistor MC1 onbit line BL0 and memory transistor MC1 on another bit line, such as BLn,while inhibiting a write on memory transistor MC1 on bit line BL1, wordline WL1 is raised to V_(cc) =3.0, volts while all other nodes are heldat V_(s) =ground. Then the p-well (bulk) is lowered to V_(negpw) =-8.0volts. Simultaneously bit lines BL0 and BLn follow the p-well toV_(negp) =-7.0 volts, but bit line BL1 follows the p-well to onlyV_(inh) =-2.0 volts. The unselected word lines, WL0, WL2, WL3 throughWL15 are driven to V_(negp) =-7.0 volts. When the unselected word linesfall to V_(negp), the channel potential in the memory transistor MC1 onbit lines BL0 and BLn will be very near V_(negp), since all of thetransistors in the NAND stack will be inverted and conductive.

A high field is thus created across the ONO dielectric in the selectedmemory transistor MC1 on bit lines BL0 and BLn which causes electrons totunnel into the traps in the silicon nitride, shifting the thresholdvoltage positively to program state. On the other hand in the memorytransistor MC1 on the bit line BL1, once the unselected gates fall athreshold voltage below V_(inh), the channel will become isolated andthe channel potential will remain near V_(inh) minus the magnitude ofthe threshold voltage of the unselected transistors. If the isolatedchannel potential changes during inhibit mode due to stray unwantedleakage, the channel can be returned to near V_(inh) by periodicallypulsing the unselected gates momentarily back above V_(inh). Theunselected transistors in this case have a high back gate bias whichshifts the threshold voltage positively, affecting the selection ofV_(inh).

Regardless of the data state, the potential difference between the gateand channel of the unselected devices is either zero or very near zero,virtually eliminating disturbs. This benefit results from using allnegative, or depletion, threshold voltages for both the program anderased states, thus eliminating the need for gate bias to overcome theprogram state threshold voltage. It is therefore apparent that thepresent invention virtually eliminates disturbs in the program mode byeliminating the need for gate bias on unselected devices.

SONOS memory cells typically have well behaved program and erasecharacteristics. Program and erase speeds are highly predictable withthe total program or erase threshold distribution typically spanning notmore than 300 mV (millivolts). There is also a highly predictablenatural charge loss over time from the silicon nitride film, and withthis charge loss, program and erase threshold voltages decay predictablyover time to the natural (no charge) threshold voltage.

FIG. 14 illustrates this threshold voltage decay versus time for anexample worst case SONOS cell in both the program and erase state. TheV_(tpmax), V_(tpmin) and V_(temax) shows the worst cast thresholdvoltage levels that cells can have and still work with the new read biasscheme. Worst case conditions typically occur when the operatingtemperature is at its highest since the charge decay is a thermallyactivated process.

Typically silicon nitride based dielectric storage technologies attainretention at 10 years with usually 100K. erase/program cycles attemperatures as high as 80° C. If product were expected to operate wellabove 80° C. or with significantly greater erase/program cycles, thecharge would decay faster. The result is that retention would probablybe less than the industry standard of 10 years if no precautions aretaken.

Referring now to FIG. 15, a fourth preferred embodiment uses a SONOSbased timer which takes advantage of the predictable threshold voltagebehavior. Such a timer element is disclosed in U.S. provisional patentNo. 60/007,062, which is incorporated herein by reference. The SONOSbased timer can be used to time-out prior to SONOS memory cell failureindicating the impending failure of SONOS memory cells in the blocks 75.

A non-volatile memory device according to the fourth preferredembodiment of the invention has a memory array 70 which includes atleast two blocks 75, each block being at least one, and preferably morethan one NAND stack units in height. The NAND stacks are not shownwithin the blocks 95'" in FIG. 15, but are shown in greater detail inFIG. 12. Associated with each block 95'" are the row decoders 72 thatdrive lines 601 across the width of the blocks 75, including word lineWL, line GSL, and an optional line SSL. The use of these lines 601within block 95'" is shown in greater detail in FIG. 12. The blocks 95'"are linked together by the bit lines 600 that also go to the page senseamps, buffers and column decoders 74. Further, blocks 95'41 are linkedtogether in common by the common reference line CSL 610, whose voltageis generated and controlled by a reference generator 76. referencegenerator 76 is required since the voltage on the common reference lineCSL is not equal to ground potential during read modes as describedabove.

Predecoded row address selection information is supplied to row decoders72 by the row predecoder 71 by way of the predecoded row address bus603. The row address lines 602 supply row input address information torow predecoders 71, and, likewise, column address lines 604 providecolumn input address information to column decoders, included in thepage sense amps, buffers and column decoders 74.

An erase/program control unit 73 is included which is controlled bywrite control lines 609 to supply Vneg1 606 to the row decoders 72,Vneg2 608 to the page sense amps, buffers and column decoders unit 74,and V_(pw) 607 to the memory array 70. Data input and output isperformed by way of data line 605.

The erase/program control unit 73 also supplies Vneg3 612 to the SONOSbased block timers 60 and the short timer 62 to reset the SONOS elementwithin these timers. The block timers 60 output to the row decoders 72to signal that a refresh operation on its associated block is enabled.Also block timers 60 output to a wired-or line, refresh 613, that signalto the timer controller 61 to refresh the block that timed-out if theshort timer 62 has also timed-out. The timer controller 61 controls therefresh operation on all parts of the memory through the timer bus 611.The timer bus 611 switches the row predecoders 71 to look at counter 63address on line 614 instead of row address 602 and tells the counter 63to reset on first refresh of word line, WL, and to count to the nextword line for subsequent word line refreshes. Also, the timer bus 611inhibits other block timers 60, if one has already timed-out. Timercontroller 61 controls the overall activity of monitoring the timer 60and short timer 62 as well as controlling a refresh mode to re-writedata stored in block 75. Counter 63, row predecoders 71, the page senseamps, buffers and column decoders unit 74 and erase/program control 73are controlled by timer controller 61 by way of the timer bus 611 togenerate row address sequences, row selections and biases during refreshmode.

Upon the time-out event in timer 60 a refresh cycle can be initiated to"refresh" the memory cells in block 75. Ideally, only a single timerwould be necessary and the entire memory would go through refresh cyclesupon time-out. In a SONOS technology, the erase/program cycle takesabout 10 milliseconds to complete and with a large array with possibly8K word lines or more, 80 seconds would be necessary to refresh thewhole array. This amount of time could be extremely taxing on a systemif done all at one time. A better solution would be to dedicate a timerto each block 95'" or groups of block 95'" containing 16, 32, 48, 64 ormore word lines corresponding to 1, 2, 3, 4 or more NAND stack units.FIG. 15, therefore, shows one timer per block and a timer controllerthat is designed to refresh only one block at a time rather than theentire memory device.

More specifically, using both FIG. 15 and FIG. 12, upon time-out, theblock timer 0 sends a signal to timer controller 61 indicating that thethreshold voltage in cells within block 0 are near their end of lifevalues. Timer controller then executes the refresh cycle on each wordline, WL, in block 0. A read mode is initiated by precharging bit linesand activating the page sense amps, buffers and column decoders unit 74to read data from a selected row. Counter 63 is initialized with thefirst row address within block 0 and then row predecoder 71 and rowdecoder 0 establish word line biases to a read all of the memory cellson word line WL0. The erase/program control 73 is then activated tofirst erase word line WL0 within block 0 and then to program the datastored in the sense amplifiers back into the memory cells. Thus the datawhich was read from the cells on word line WL0 is refreshed to beginningof life threshold voltages.

The timer controller 61 then continues this refresh cycle for theremaining word lines, WL1, WL2 through WL15, each time incrementing thecounter 63 so that the row decoder 0 selects the proper row. Once thelast row has been refreshed, the SONOS timer element in timer 0 is resetby using Vneg3. With 16 word lines in a block, the total time to refreshthe memory cells on each word line would be 160 ms, which is much moresystem and user friendly than 80 seconds of refresh cycles.

How often refresh cycles are required will depend on the rate at whichcharge decays from the silicon nitride. The block timer 60 is designedsuch that its SONOS timing element experiences the same conditions asthe memory cells within its associated block 75. Under nominalconditions Timer 60 may take tens of years to time-out. However, undermore severe conditions, such as high temperature, high endurance and/orhigh disturbs, timer 60 could time-out as often as every month. Here theprobability of simultaneous time-out among the various timer 60 is high,especially upon power-up when the device is unpowered for extendedperiods of time. In the worst case, the entire device could requirerefresh upon power-up, delaying useful operation for minutes. To preventthis long continuous refresh a short timer 62 is provided which musttime-out between the refresh of each block 60. Thus after a block 60 isrefreshed, the timer controller 61 resets the SONOS timing element inshort timer 62 using Vneg3. Thereafter, the timer controller 61 isprecluded from refreshing a subsequent block 95'" until short timer 62times out again. The time-out period of the short timer 62 will beminutes to hours, depending on the application.

Although the invention has been described and illustrated with a certaindegree of particularity, it is understood that the present disclosurehas been made only by way of example, and that numerous changes in thecombination and arrangement of parts can be resorted to by those skilledin the art without departing from the spirit and scope of the invention,as hereinafter claimed.

What is claimed is:
 1. A non-volatile semiconductor device comprising:asemiconductor substrate; data transmission bit lines arranged on saidsubstrate; a memory cell section including a plurality of memory units,each connected on a first end to one of said bit lines and on a secondend to a common reference node, at least one said memory unit comprisingaddressable memory transistors, each of said memory transistors having asource, node a drain, node a gate, and a charge storage layer that hasprogrammable memory states that produce a first depletion thresholdvoltage of magnitude less than a magnitude of a supply voltage when thememory transistor is programmed and a different threshold voltage whenthe memory transistor is erased; and at least one timer circuit togenerate an output logic signal to request a data refresh operation nolater than when charge stored on charge storage layers associatedtherewith can no longer be detected, said timer circuit comprising atransistor timing element having a source, a drain, a gate, and a chargestorage layer that has programmable memory states.
 2. The device ofclaim 1 wherein said device further comprises biasing circuitry forapplying selected read biasing voltages to said memory units including areference voltage of magnitude no greater than the magnitude of saidsupply voltage and greater than the magnitude of said first thresholdvoltage, the reference voltage being applied to said reference node, anda voltage greater than said reference voltage applied to said first endof said memory unit;sensing circuitry for sensing a current generated atsaid first end of said memory unit in accordance with the programmablestate of said charge storage layer of said addressable memorytransistor; circuitry for applying selected erase biasing voltages tosaid memory units to selectively erase memory transistors connected to asingle selected word line; and circuitry for applying selected writebiasing voltages to said memory units to selectively write data intomemory transistors wired in common on a single selected word line. 3.The device of claim 2 wherein said device further comprises a timercontroller to provides means for initiating and controlling theexecution of said data refresh operation once actuated by said timercircuit, said refresh operation comprising a controlled sequence of atleast first reading selected addressable memory transistors to determinethe current programmed state of said charge storage layer of each ofsaid selected addressable memory transistors, second erasing saidselected addressable memory transistors, and third programming saidselected addressable memory transistors to restore said currentprogrammed state.
 4. The device of claim 3 wherein said device furthercomprises means to electrically partition said plurality of memory unitsinto separate groups forming at least two blocks;means for independentlys electing blocks for a block refresh operation, said block refreshoperation constituting a refresh operation performed on no more than thememory transistors within a selected block; and a t least two timercircuits each being uniquely associated with one of said blocks forindependently actuating said timer controller to execute said blockrefresh operation on said selected block associated therewith.
 5. Thedevice of claim 1 wherein each of said addressable memory transistorscomprise a SONOS tunneling metal insulator semiconductor field effecttransistor.
 6. The device of claim 1 wherein each of said memory unitscomprise series connected addressable memory transistors and at leastone selection transistor connected in series to the second end toconnect said second end of each of said memory units to said referencenode.
 7. The device of claim 1 wherein said substrate has a firstconductivity type and said source and drain nodes are semiconductorregions of a second conductivity type.
 8. The device of claim 1 whereinsaid substrate has a first conductivity type and said source and drainnodes are semiconductor regions of a first conductivity type; andwherein said memory cell section further comprises a first well regionof a second conductivity type formed in said substrate as to surroundsaid memory units.
 9. The device of claim 8 wherein means is providedfor connecting said substrate to said supply voltage and for connectingsaid first well to a supply reference voltage during a read operation.10. The device of claim 1 wherein said substrate has a firstconductivity type and said source and drain nodes are semiconductorregions of a second conductivity type; and wherein said memory cellsection further comprises a first well region of a first conductivitytype formed in said substrate as to surround said memory units andwherein said device further comprises an additional -second well regionof the second conductivity type formed in said substrate as to surroundat least said first well region.
 11. The device of claim 10 whereinmeans is provided for connecting said substrate to a supply referencevoltage and for connecting said second well to said supply voltage, andfor additionally connecting said first well to said supply referencevoltage during a read operation.